Dr. Janusz Rajski
Chief Scientist and
Director of Engineering
Mentor Graphics Corporation
Wilsonville, OR 97070, USA
Janusz Rajski received the M.S. degree from the Technical
University of Gdañsk, Poland, in 1973, and the Ph.D. degree
from the Technical University of Poznañ, Poland, in 1982, both
in electrical engineering. In 1984, he joined McGill University,
Montreal, Canada, where he became an associate professor in
1989. In 1995, he accepted the position of chief scientist at
Mentor Graphics Corporation, Wilsonville, Oregon. His main
research interests include testing of VLSI systems, design for
testability, built-in self-test, and logic synthesis. He is co-author
of Arithmetic Built-In Self-Test for Embedded Systems published
by Prentice Hall in 1997, and co-recipient of the 1993 Best Paper
Award for the paper on synthesis of testable circuits published in
the IEEE Trans. on CAD. He has served on technical program
committees of various conferences including International Test
Conference. Dr. Rajski is a co-founder of the International Test
Synthesis Workshop.
The Challenges of Structural Test in Nanometer Technologies

Why is nanometer technology different than any other previous smaller geometry process?
In the past, most DFT challenges could be predicted by monitoring Moore's law of device
complexity. Nanometer technology is affecting DFT in several new ways. Copper process
introduces new challenges in test quality. Low yield and new types of defects require much larger
number of patterns to achieve acceptable quality. As a result, the volume of test data required by
conventional scan and ATPG grows much faster than the device gate count. More complex fault
models, bigger designs, and larger pattern sets create problems of significantly bigger
computational complexity. These challenges require new embedded test solutions that improve
quality, reduce cost of test, and are computationally very efficient.

Wolfgang Rosenstiel is the professor of computer engineering at
the University of Tuebingen and director of the System Design in
Microelectronics Department at the Computer Science Research
Center Karlsruhe (FZI). Prior to this appointment he was research
assistant and assistant professor in the Computer Science
Department at the University of Karlsruhe (1980 - 1986), and
then the head of research group "Automation of Circuit Design"
at FZI. His research interests include high level synthesis,
hardware software codesign, computer architecture, parallel
computing, and neural nets. He received diploma in informatics
from University of Karlsruhe in 1980, and Ph.D. degree from the
same university in 1984. He was the program chair of Eurodac
95, VLSI95, Eurodac 94, EDAC92, HLSW91, and general chair
of Eurodac 97 and HLSW92. He is a member of editorial board
of DAES-Journal and member of IFIP 10.5 working group.
Prof. Wolfgang Rosenstiel
Eberhard-Karls-Universität Tübingen
Wilhelm-Schickard-Institut für Informatik
72076 Tübingen
Platform Based Design of Embedded Systems in SystemC

Designing the most appropriate system architecture is key to an efficient implementation of
complex algorithms such as those found in advanced applications. Over the years, it has
always been recognized that raising the level of abstraction at which the creative work was
done was the most effective method for improving design efficiency. Today's design
methodology for embedded systems is often platform based. Finding the best
algorithm/architecture trade-off is important for this design technique. SystemC is well suited
to model and specify both functions as well as architectures. This talk will therefore especially
explain how SystemC can be used for platform based design.

John Hayes holds the Claude E. Shannon Chair in the Electrical
Engineering and Computer Science Department at the University
of Michigan, where he has been since 1982. Prior to that, he
was with the University of Southern California. He teaches and
conducts research in the areas of computer-aided design and
testing, fault tolerance, embedded computer architectures, and
quantum computing. He is the author of several texts including
"Computer Architecture and Organization," (3rd ed. McGraw-
Hill 1998), and numerous research papers. Dr. Hayes received
the B.E. degree from the National University of Ireland, and the
M.S. and Ph.D. degrees from the University of Illinois at
Champaign-Urbana. He is a Fellow of IEEE and ACM.
Prof. John P. Hayes
Advanced Computer Architecture Laboratory
Dept. of Electrical Engineering & Computer Science
University of Michigan
Ann Arbor, MI 48109, USA
Testing Quantum Circuits

This talk will survey the development of quantum circuits, with emphasis on their failure modes
and testing requirements. Some methods for error correction and recovery that have been
developed specifically for quantum circuits will be discussed. Finally, the physical implementation
of quantum circuits will be considered, along with the prospects for achieving practical
quantum computers.